1. Field of the Invention
The present invention relates to a semiconductor device.
2. Background of the Related Art
With the continuing reductions in power consumption in power conversion devices, there are considerable expectations for a reduction in power consumption in power devices that fulfill a central role in power conversion devices. Among these power devices, the use of voltage-driven insulated gate bipolar transistors (IGBTs) such that low on-state voltage can be realized by a conductivity modulation effect, and such that current can easily be controlled by the voltage applied to the insulated gate, is becoming widespread. Planar gate IGBTs and trench gate IGBTs are publicly known as these IGBTs.
A planar gate IGBT has a MOS gate (an insulated gate formed of metal-oxide-semiconductor) structure formed of a gate electrode provided on a substrate front surface. A trench gate IGBT has a MOS gate structure formed by a gate electrode (hereafter referred to as a trench gate) acting as a control electrode being embedded inside a trench provided on a substrate front surface side. As a trench gate IGBT is such that a channel is formed along both side walls of the trench, the channel density is greater, and the on-state voltage lower, than in a planar gate IGBT, wherein a channel is formed along the substrate front surface. Therefore, commercial applications for trench gate IGBTs have been increasing in recent years.
A description will be given of the configuration of a general trench gate IGBT, giving as an example an n-channel IGBT wherein a trench gate is disposed in a stripe form planar layout extending in a direction (the depth direction of the drawing, hereafter referred to as the longitudinal direction) perpendicular to the direction in which the trenches are aligned (hereafter referred to as the lateral direction). FIG. 7 is a sectional view showing the structure of a general trench gate IGBT. A section crossing the trench gate of the general trench gate IGBT in the lateral direction is shown in FIG. 7. As shown in FIG. 7, a p-type layer 103 is provided on the front surface side (n−-type drift layer 102 side) of a silicon substrate (semiconductor chip) formed by an n−-type drift layer 102 being deposited on the front surface of a p+-type semiconductor substrate that forms a p+-type collector region 101.
An n+-type emitter region 104 is selectively provided inside the p-type layer 103. A trench 105 is provided penetrating the n+-type emitter region 104 and p-type layer 103 in the depth direction from the surface of the n+-type emitter region 104, reaching the n−-type drift layer 102. A gate electrode 107 is provided across a gate insulating film 106 inside the trench 105. The gate electrode 107 is electrically isolated from an emitter electrode 109 by an interlayer dielectric 108 that covers an upper portion of the gate electrode 107. The emitter electrode 109 is in conductive contact with a p-type base region 111, to be described hereafter, and the n+-type emitter region 104 via contact holes provided in the interlayer dielectric 108.
The p-type layer 103 is divided by a plurality of the trench 105 into the p-type region (p-type base region) 111, in which the n+-type emitter region 104 is provided, and a p-type region of floating potential (hereafter referred to as a floating p-type region) 112, in which the n+-type emitter region 104 is not provided. The floating p-type region 112 is electrically isolated from the emitter electrode 109 by the interlayer dielectric 108, which covers the surface of the p-type layer 103. Also, the floating p-type region 112 is electrically isolated from the n−-type drift layer 102 by the p-n junction between the floating p-type region 112 and the n−-type drift layer 102, and is isolated from the gate electrode 107 by the gate insulating film 106. A collector electrode 110 is provided on the back surface of the p+-type semiconductor substrate.
Next, a description will be given of an operation at a time of turning on, when the trench gate IGBT shifts from an off-state to an on-state. Normally, the emitter electrode 109 is in a grounded state, or in a state wherein negative voltage is applied. The collector electrode 110 is in a state wherein positive voltage is applied. Even in a state wherein a voltage higher than that applied to the emitter electrode 109 is applied to the collector electrode 110 in this way, the p-n junction between the p-type base region 111 and n−-type drift layer 102 is reverse biased when voltage applied from a gate drive circuit (not shown) via a gate resistor to the gate electrode 107 is lower than a threshold value, because of which no current flows between the emitter and collector. That is, the IGBT maintains an off-state.
Meanwhile, when voltage exceeding the threshold value is applied from the gate drive circuit via the gate resistor to the gate electrode 107, a charge begins to accumulate in the gate electrode 107, simultaneously with which a region of the p-type base region 111 opposing the gate electrode 107 across the gate insulating film 106 inverts to n-type, whereby a channel region is formed. Therefore, electrons emitted from the emitter electrode 109 pass through an n-type region formed of the n+-type emitter region 104 and channel region, and are implanted into the n−-type drift layer 102. By electrons being implanted into the n−-type drift layer 102, the p-n junction between the p+-type collector region 101 and n−-type drift layer 102 is forward biased, and holes are implanted from the collector electrode 110 into the n−-type drift layer 102, because of which current flows between the emitter and collector. That is, the IGBT shifts to an on-state. The voltage drop between the emitter electrode 109 and collector electrode 110 in the on-state is the on-state voltage.
Next, a description will be given of an operation at a time of turning off, when the trench gate IGBT shifts from an on-state to an off-state. By the voltage applied to the gate electrode 107 (the voltage between the emitter electrode 109 and gate electrode 107) being reduced to the threshold value or lower, the charge accumulated in the gate electrode 107 is released toward the gate drive circuit via the gate resistor. At this time, by the portion of the p-type base region 111 inverted to n-type returning to p-type and the channel region disappearing, the supply of electrons from the emitter electrode 109 to the n−-type drift layer 102 stops. Therefore, the supply of holes from the collector electrode 110 to the n−-type drift layer 102 also stops, because of which electrons and holes accumulated inside the n−-type drift layer 102 are expelled into the collector electrode 110 and emitter electrode 109 respectively, or are annihilated owing to recombination, whereby the current stops flowing between the emitter and collector. That is, the IGBT shifts to an off-state.
Various configurations for further reducing the on-state voltage of the trench gate IGBT have been proposed. For example, an IGBT called an IEGT (Injection Enhanced Gate Bipolar Transistor), which includes a characteristic of a limit near the on-state voltage of a diode, is publicly known, for example, refer to PTL 1 (JP-A-5-243561, FIG. 101). An IEGT is such that an electron injection enhancement (IE) effect is increased by the area of contact between the n+-type emitter region and p-type base region and the emitter electrode being reduced by one portion of the surface of the n+-type emitter region and p-type base region being covered with an insulating film so that the portion covered with the insulating film and the emitter electrode do not come into contact.
Operations of the IEGT are basically the same as those of the heretofore described trench gate IGBT, but the IEGT is such that holes accumulated in the n−-type drift layer in the vicinity of the p-type base region are unlikely to be expelled into the emitter electrode in the portion wherein the surface of the n+-type emitter region and p-type base region are covered with an insulating film, and holes accumulate in this portion. Therefore, the IEGT is such that the carrier concentration distribution of the n−-type drift layer can be increased to a state near the carrier concentration distribution of a diode, and the on-state voltage can be reduced further than that of a normal trench gate IGBT.
However, as well as low on-state voltage, high-speed switching characteristics are also required of a power device used in a power conversion device, meaning that improvement of high-speed switching characteristics is also one important task. The IEGT is such that, as holes are unlikely to be expelled into the emitter electrode, switching characteristics are inferior to those of a normal trench gate IGBT. Also, as the trench gate IGBT and IEGT are such that trench gate structures are distributed densely, the gate-emitter capacity also increases. As heretofore described, it is necessary for the switching operations of the IGBT that a charge is accumulated in the gate-emitter capacitor when shifting from an off-state to an on-state, and that the charge accumulated in the gate-emitter capacitor is released when shifting from an on-state to an off-state.
Consequently, when the gate-emitter capacitance is high, there is an increase in the time for charging or discharging the gate-emitter capacitor when carrying out a switching operation, and switching loss also increases, because of which there is a problem in that there is an increase in the occurring loss of the power device. The occurring loss of the power device is the sum of steady loss determined by on-state voltage and switching loss occurring when carrying out a switching on-operation and off-operation. Therefore, reducing gate-emitter capacitance, which is a cause of switching loss occurring, is an important task. An IGBT including the floating p-type region 112 electrically isolated from the emitter electrode 109 by the interlayer dielectric 108, as shown in FIG. 7, has been proposed as an IGBT wherein this kind of problem is eliminated, for example, refer to PTL 2 (JP-A-2001-308327, FIG. 1).
In PTL 2, owing to the floating p-type region 112 being provided, holes implanted from the collector side into the n−-type drift layer 102 when in an on-state are unlikely to be expelled into the emitter electrode 109. Therefore, holes accumulate in the floating p-type region 112, and the carrier concentration distribution of the n−-type drift layer 102 is increased to a state near the carrier concentration distribution of a diode. Also, in PTL 2, the gate-emitter capacitance is reduced by a trench gate structure that does not act as a control electrode not being provided in the floating p-type region 112, whereby a reduction in the time for charging and discharging and a reduction in switching loss are achieved.
Also, a device, which is a semiconductor substrate, including a plurality of cell structures that include a peripheral diffusion region formed on the outer side of an isolation structure, a base region formed inside an element region, divided by an isolated trench gate, and having an emitter region in a surface portion, and an emitter electrode connected to the emitter region and base region, a dummy base region, neighboring the cell structure, that is a base region that does not have an emitter region connected to the emitter electrode in a surface portion, and a connection portion that electrically connects the peripheral diffusion region to the emitter electrode, has been proposed as an IGBT such that ejection of residual carriers in a chip peripheral region when turning off is enhanced, and shutoff resistance is increased, for example, refer to PTL 3 (JP-A-2006-5248). The IGBTs of PTL 2 and 3 include a floating state mesa region sandwiched by trench gates that act as control electrodes.
However, it is reported as a problem common to the kinds of IGBT including the floating p-type region 112 shown in PTL 1 to 3 that there is room for improvement in the turn-on characteristics, for example, refer to NPL 1 (M. Yamaguchi and 7 others, “IEGT Design Criterion for Reducing EMI Noise”, Proceedings of 2004 International Symposium on Power Semiconductor Devices & ICs, May, 2004, Pages 115 to 118) and NPL 2 (Y. Onozawa and 5 others, “Development of the next generation 1200V trench-gate FS-IGBT featuring lower EMI noise and lower switching loss”, Proceedings of the 19th International Symposium on Power Semiconductor Devices & ICs (Cheju), May 27 to 30, 2007, Pages 13 to 16). An IGBT including the floating p-type region 112 is such that excess holes accumulate in the floating p-type region 112 when turning on, and the potential of the floating p-type region 112 rises. An input capacitor is charged by a displacement current caused by the potential rise (=C·dV/dt, wherein C is the capacitance (feedback capacitance) of the gate insulating film 106, and dV/dt is the temporal rate of change of the collector voltage), and the gate voltage rises, because of which switching speed when turning on increases. Normally, the switching speed (collector current rate of change di/dt) is controlled by inserting a gate resistor in series with the gate electrode 107, but in the case of an IGBT including the floating p-type region 112, there is a problem in that, even when the gate resistance is increased, the switching speed when turning on cannot be reduced to a predetermined value.